1. Field of the Invention
The present invention is related to a semiconductor device provided with a Boundary-Scan test circuit.
2. Prior Art
To facilitate the testing of an electronic device, such as an integrated semiconductor circuit, or a circuit board such as a printed circuit board containing a plurality of integrated semiconductor circuits or even a group of boards, a testing technique called as xe2x80x9cBoundary-Scanxe2x80x9d has been developed.
FIG. 1 is a block schematic diagram of a circuit board design making use of a Boundary-Scan test circuit according to the prior art. In FIG. 1, each IC chip 102 mounted upon a circuit board 101 is provided with Boundary-Scan cells embedded therein which are connected in series with each other in order to form a scan path. Furthermore, a single elongated scan path is formed by serially connecting the Boundary-Scan cells of the respective chips on the circuit board 101. As a result, there is formed access to the IC chips 102 by making use of the scan path for inputting and outputting data for test from a scan-in port to a scan-out port in order to test wiring connection and so forth. It is therefore possible to conduct tests of detecting short or open circuits and other tests even in the case of a packaging substrate with high density components on which it is difficult to make physical (i.e., ohmic) contact therewith by means of a test probe.
FIG. 2 is a block diagram of a Boundary-Scan test circuit according to the prior art. In the figure, the minimum requirement for the Boundary-Scan test circuit is provision of a Test Access Port (TAP) controller 104, an instruction register 105 capable of serving as part of a scan path, an instruction decoder 110 for decoding an instruction as loaded onto the instruction register 15 and a test data register system 106 capable of serving as part of a scan path. The TAP controller 104 functions as a master controller for controlling the overall operation of the Boundary-Scan test circuit. One register of the test data register system 106 is selected by an instruction loaded onto the instruction register 105. The test data registers of the test data register system pursuant to the JTAG (for Joint Task Action Group) standard are the Boundary-Scan registers 107, the ID-Code registers 108 and the bypass registers 109.
FIG. 3 is a circuit diagram of a Boundary-Scan register according to the prior art. The Boundary-Scan register 107 is composed of a plurality of BS circuits 110 connected in series to each other for performing required operations such as serial shift operation through external pins or pads in accordance with the sampling instruction of the JTAG standard. FIG. 4 is a block diagram of the BS circuit 110 as illustrated in FIG. 3. In the figure, each BS circuit 110 is composed of a multiplexer 112 for selecting one of data PI given through the pad 111 and data SI inputted by the scan operation, and a register 113 for latching the data as selected by the multiplexer 112 in synchronism with the clock signal CKDR. In general, the BS circuits 110 has to perform exchanging data with the respective pads 111 so that the number of the BS circuits 110 corresponds to the number of the pads 111.
FIG. 5(A) is a block diagram of the ID-Code register 108 as illustrated in FIG.3. The ID-Code register 108 is composed of a plurality of ID circuits 114 connected in series to each other for electrically reading out the ID code of each chip. The ID code contains information of address, depth, I/O-Width, interface, and so forth. FIG. 5(B) is a block diagram of the ID circuit 114. In the figure, the ID circuit 114 is composed of a multiplexer 115 for selecting one of a data bit CI of an ID code represented by a high level (the electric power source level) or a low level (the ground level) and data SI inputted by the scan operation in accordance with a selection signal (SFDR), and a register 116 for latching the data as selected by the multiplexer 115 in synchronism with the clock signal CKDR. For example, in the case that the ID-Code register is provided to latch 32-bit data, it is composed of 32 equivalent circuits of the ID circuit 114.
The bypass register 109 is provided in order to bypass other registers of the test data register system. FIG. 6 is a block diagram of the bypass register 109 consisting of a negative AND gate 117 and a register 118 for latching the data as outputted by the negative AND gate 117 in synchronism with the clock signal CKDR.
In the case that a Boundary-Scan test circuit is designed in accordance with the JTAG standard, there have to be provided with these three types of the test data registers as illustrated in FIG. 7 which is a block diagram of the test data register system in accordance with the prior art.
One of the shortcomings of the LSIs with the test data register system of this kind is an area penalty. The overhead is therefore the area occupied by the Boundary-Scan test circuit which is provided only for the purpose of providing testability in addition to the proper of the LSI circuit for required functions. Particularly, the test data register system as illustrated in FIG. 7 requires a large amount of hardware resource (registers) and therefore results in most of the area penalty.
In order to face with the problem, it is proposed in Publication of Unexamined Patent Application No.Hei7-104035 to use one register as the Boundary-Scan register and the ID code register and to be switched with another register functioning as the bypass register. Also, Publication of Unexamined Patent Applications No.Hei7-151829 and No.Hei8-136619 disclose techniques to use one register as the Boundary-Scan register and the ID code register in order to reduce the hardware amount of the test data register system.
On the other hand, there is a need to make it easy to test semiconductor devices even in the fields handling a variety of semiconductor integrated circuits other than ASIC in the recent years. For example, it is desired to improve testability by providing the Boundary-Scan test circuit within chips in the case of the semiconductor storage devices. However, since the target is the class of ASICs in the case of the above described prior art Boundary-Scan test circuit, what can be extracted from a chip is only the ID code data which is hardwired data fixedly implemented within semiconductor chips, e.g., by selectively melting and disconnecting fuses. Because of this, in the case that the Boundary-Scan test circuit is implemented into semiconductor storage devices, the testability is not effectively improved by information only of the ID code given from the Boundary-Scan test circuit.
The present invention has been made in order to solve the shortcomings as described above. It is an important object of the present invention to provide a semiconductor device provided with a compact Boundary-Scan test circuit.
It is another associated object of the present invention to provide a semiconductor device provided with a Boundary-Scan test circuit capable of providing extended data useful for testing the semiconductor device.
In brief, the above and other objects and advantages of the present invention are provided by a new and improved semiconductor device provided with a Boundary-Scan test circuit comprising:
an instruction register for latching an instruction required for carrying out a Boundary-Scan test of the semiconductor device;
an instruction decoder for decoding an instruction as loaded onto the instruction register; and
a test data register system controlled by control signals output from the instruction decoder;
the test data register system comprising a Boundary-Scan test register composed of bit elements serially connected to each other in the form of a scan path and each of which is connected respectively to one of pads of the semiconductor device,
wherein part of the bit elements of the Boundary-Scan test register functions also as an ID-Code register which is capable of selectively outputting either of the ID-Code of the semiconductor device and extended data.
Also, in accordance with a preferred embodiment of the present invention, the instruction register functions as a scan path through which the instruction is loaded onto the instruction by scanning operation.
Furthermore, in accordance with a further preferred embodiment of the present invention, the extended data includes information for the manufacturer of the semiconductor device.
Furthermore, in accordance with a further preferred embodiment of the present invention, the extended data is indicative of whether or not there are available spare elements, the use of a fuse, or redundancy information about the spare elements such as redundancy addresses.
Furthermore, in accordance with a further preferred embodiment of the present invention, a Test Access Port controller for controlling operation of the Boundary-Scan test circuit is provided.
Furthermore, in accordance with a further preferred embodiment of the present invention, a multiplexer which selects and outputs one of the output signal of the initial bit element and the output signal of the last bit element in accordance with a control signal as generated from the instruction decoder is provided.
In accordance with another aspect of the present invention, a semiconductor device provided with a Boundary-Scan test circuit comprising:
an instruction register for latching an instruction required for carrying out a Boundary-Scan test;
an instruction decoder for decoding an instruction as loaded onto the instruction register; and
a test data register system controlled by control signals output from the instruction decoder;
the test data register system comprising a Boundary-Scan test register composed of bit elements serially connected to each other in the form of a scan path and each of which is connected respectively to one of pads of the semiconductor device,
wherein an initial bit element of the Boundary-Scan test register functions also as a bypass register for bypassing the subsequent bit elements of the Boundary-Scan test register.
In accordance with a further aspect of the present invention, a semiconductor device provided with a Boundary-Scan test circuit comprising:
an instruction register for latching an instruction required for carrying out a Boundary-Scan test;
an instruction decoder for decoding an instruction as loaded onto the instruction register; and
a test data register system controlled by control signals output from the instruction decoder;
the test data register system comprising a Boundary-Scan test register composed of bit elements serially connected to each other in the form of a scan path and each of which is connected respectively to one of pads of the semiconductor device,
wherein part of the bit elements of the Boundary-Scan test register functions also as an ID-Code register while an initial bit element of the Boundary-Scan test register functions also as a bypass register for bypassing the subsequent bit elements of the Boundary-Scan test register.
Other and further objects and features of the present invention will become obvious upon an understanding of the illustrative embodiments about to be described in connection with the accompanying drawings or will be indicated in the appended claims, and various advantages not referred to herein will occur to one skilled in the art upon employing of the invention in practice.